Timing and Control Description

Rowboat Encrytion Chip
http://www.owlnet.rice.edu/~pickettc/elec422/control.html Frank Alejano
John Cusey
Chris Pickett

I. Some Initial Comments

Most of the substantive portion of this is outlined on the attached finite state machine diagram that is attached. Unfortunately, we are still researching the optimal way to put diagrams such as these online; the present method that we are using is extremely slow and tedious, so this diagram is not yet visible from the homepage. It is coming, however.

Due to the large number of control signals that the state machine will generate, we have not included what all of them will be at every state in the state machine. If a control signal state is not specified, it either a) is a don't care (as in the case in_con_0, the control for the input demux when the state machine is in the middle of counting the rounds of encryption); or b) it is tied to a disabling voltage (as would be IRWE0' when we are in the state that latches the output registers).

Finally, as will become immediately obvious when one takes a look at the state diagram, we have shown a Moore Machine implementation for our control. Since the meg tool in Magic implements Mealy Machines, we will need to convert our FSM into a Mealy FSM. We stayed with the Moore representation here because we felt that it was easier to conceptualize. The conversion between the two should result in fewer states in the machine; for example, presently we have thirty-two states that perform the eight rounds of encryption. These 32 states are essentially 4 states repeated eight times. The only difference is the round of encryption that the machine is on (as represented by a three-bit counter). In a Mealy Machine implementation, it might be possible to reduce these 32 states down to 4. This is something that we will consider when we actually write the meg file implementing the control FSM.

II. The Timing

As you might suspect, we will a non-overlapping two-phase clock. Our clocking discipline will follow the scheme outlined in the Noice and Karplus papers. Essentially, our chip will latch inputs, route the latched inputs to other internal latches, latch them there, run the results through some logic a number of times, latching intermediate results, and finally latch the outputs. As far as timing goes, the critical region of the data path is the area where the data is taken from a latch and run through logic, with the results being latched for the next pass (i.e., the section during the rounds of encryption). In the other sections, where we are just shuffling data around to different latches, all we have to do is ensure that the clocking signals successive latches in the data path are valid with respect to different phases of the clock, i.e., that if data goes from Latch X to Latch Y, then data_X must Va at least and data_Y must at least Vb. This is not a problem because if Latch X and Latch Y are clocked with different phases of the clock, then the output of Latch_X MUST be VaSb and the output of Latch Y MUST be VbSa, which is what we want.

For the rounds of encryption, however, things are a little more difficult. The data path is thus: Latch X -> Logic -> TempLatch -> Latch X. The input to Latch X must be at least Va, meaning that the output will be VaSb. This means that all input to the xor logic which does not come from Latch X must be at least Vb; fortunately, the only inputs to the logic that wouldn't come from the latch would come from the FSM, meaning that it would be Vb. The output of the logic would thus also be Vb, meaning that the output of the TempLatch would be VbSa, which is what we want for the input to Latch X. This is good.

III. The States

The finite state machine will consist of 40 different states (see attached). It will receive 3 input signals (E/D', which will tell it whether encryption or decryption is desired; D/K', which will tell it whether the user is entering data or a key; and RST', which will tell it whether it needs to go back to the first state); E/D' and D/K' will be latched on the first clock cycle after the FSM resets, and changes in them after this point will not be seen until the FSM is again reset. Changes in RST' will be seen during the clock cycle in which they occur, and if RST' is brought low, then the chip will essentially stop wherever it is and return to the initial state; whatever it has been doing since the last reset will be lost. Since there are 40 states in the FSM, we will need a six-bit binary number to represent each state. Although these are not strictly of interest to the user of the chip, they will be useful for testing and debugging purposes and will be bonded out as output signals. In addition, an OptValid' signal, which goes low when the data on the output pins is valid, will also be an output from the FSM.

In addition to these externally-seen outputs, the FSM will generate a number of control signal; these are detailed on the attached diagram. Essentially, every mux or demux has a control signal, every latch has an active-low write enable signal, and the logic that determines what key to use in the rounds of encryption receives signals telling it whether the chip is in encrypt or decrypt mode and what round of encryption the chip is on. Strictly speeking, it probably would have been possible to have done this with fewer states or with fewer control signals -- if we had really wanted to, we might have been able to get away with no control at all; however, this would make the project somewhat uninteresting. Since this is, after all, an academic exercise, we don't feel too guilty about our unnecessary complexity.

IV. The Signals

For your convenience, we have listed all of the signals used and what their purpose is:

RST': Resets the FSM to the first state. It is active low enable, and (despite the fact that this is not stated on the FSM diagram), having RST' go low at any time will result in the FSM to be put into state IR0.

IRWE0', IRWE1': These are the write enable signals for the input registers. They are active low.

DRWE0', DRWE1': These are the write enable signals for the data registers. They are active low.

KRWE0', KRWE1': These are the write enable signals for the key registers. They are active low.

ORWE0',ORWE1': These are the write enable signals for the output registers. They are active low.

TRWE0': This is the write enable signal for the temporary register. It is active low.

in_con_0: This is the control signal for the demux at the input. When this is low, the input data is routed to Input Register 0. When it is high, input data is routed to Input Register 1.

in_con_1: This is the control signal for the second demux in the data path. If this is low, then the data from the Input Registers is routed to the Key Registers; otherwise, it is routed from the Input Registers to the Data Registers.

out_con: This is the control signal that controls the output mux. If it is low, then the data from Output Register 0 is routed to the output pins. Otherwise, the data from Output Register 1 is routed to the output pins.

cnt_0, cnt_1, cnt_2: These are the signals that tell the encryption rounds how many rounds of encryption have been done so far.

en_or_de: This signal is identical to the E/D' input signal.

October 3, 1995