VLSI Design Project

A Simple Calculator

Basic Facts
Functional Description
Testing Results
Reasons for Chip Failure
Speed Test Results
Submitted by...
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This page has been accessed times since April 23, 1996.

Basic Facts

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Functional Description of the Chip

This project designed and tested an 8 bit calculator that can compute addition, subtraction, NOT, AND, OR, and XOR as well as shift left and right up to 4 bits and append up to 4 bits to the shifted number. Furthermore, this 8 bit calculator has an output feedback loop so the output can be remembered and operated on in subsequent clock cycles.

The 8 bit numbers for addition and subtraction operations are in 2's complement form

The chip is built from several subcells. The main operation blocks are the arithmetic logic unit which computes the logic functions as well s the addition and subtraction, a block for shifting the input to the left and a similar block for shifting the input to the right. The arithmetic logic unit can be further broken down into two 4 bit ALUs with a carry in and a carry out pin.

The inputs are latched, and the operation codes are fed inot a decoder which in turn activates the appropriate operation. The flow of the data in the chip is controlled by a small PLA which dictates when to reset the latches, when to load the data, and when to feedback the output.

The output from each operation is multiplexed to ensure that the output from the desired function is allowed to pass through and then latched, giving the user the option of feeding the input in the next clock cycle.

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Testing Results

Out of the 4 chips that we received, 2 were completely functional, the other two were partially functional.

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Reasons for Chip Failure

For one of the chips, it was because the OUT2 pin on the output was stuck at "1". The error we felt was located in the output latch because the otuput was consistently high across all the operations. We feel that since this error was not present in the other three chips, that this is probably the result of a fabrication error.

For the chip that was partially functional, the outputs that were incorrect were all exhibited in the Right shift and Left shift operations.

Right shift fails when you want to shift more than 2 bits and you want to add a "1" as the bit corresponding to the IN1 input to the shifter, because IN1 is stuck at zero for the right shift bank of shifters.

Left shift fails when you want to shift more than 1 bits and you want to add a "1" as the bit corresponding to the IN0 or IN2 input to the shifter, because both IN0 and IN2 are stuck at zero for the left shift bank of shifters.

We feel that the errors are due to fabrication error because the error does not repeat itself in the other three chips.

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Speed Test Results

The chip was tested at 34MHz sampling frequency. The chip worked when tested with a clock cycle greater than 117.6 ns and failed when tested with a clock cycle of 58.8ns. This is consistent with our SPICE simulations which predicted that the chip would fail at around 70ns. Since Omnilab is not capable of measuring clock cycles in between 117.6ns and 58.8ns, we were unable to test the chip in that interval to get a more precise result.

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Submitted by

Submitted by Daniel Go and Jing Zhao.
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Download our reports!

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Chip testing presentation (postcript, 10 mbs)
Chip testing report (postcript, 5mbs )
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