Elec 422 VLSI Design Project - Group D presents:

Asynchronous Communications Interface Adapter

Design Team Members: Jenie Fu, Sanjit Ganguli, Jason Kincaid

Abstract

The goal of this project is to implement a telecommunications interface chip that serves as an interface between the transmitting terminal and the communications network and medium. This system will mimic the function of an Asynchronous Communication Interface Adapter (ACIA) and will be designed using VLSI Design Layout tools and 2 micron technology. Our design fits into a standard communication system consisting of a terminal which outputs the information to be sent, a DTE (data terminal equipment) in the form of an ACIA, and a DCE (data communication equipment) in the form of a modem. One limitation of this system is that it will only support simplex communication. The DTE on the receiving end will be built by Group E, our sister group.

Features and Functional Synopsis

This device will receive data from the terminal in 8-bit parallel ASCII coded form. Our ACIA will support the following features:




data conversion from parallel to serial form

data compression from 8-bit ASCII to 6-bit form

addition of parity bits for transmission error checking

correction of transmission errors by retransmission

correct speed clocking to match receiving end


Data flow will occur as follows. Upon request, a 7 bit ASCII encoded character will be loaded from the computer into the system. Once loaded, it will be fed through the data compression and error coding unit, where the word will be condensed into a 6 bit representation and then 2 bits of error coding will be appended. The error coding will include one bit for even parity and one bit for odd parity, thereby preventing transmission errors. This new 8 bit sequence will then be loaded into the "New" register and will await a transmission signal from the receiving chip. Once transmitted, the word will be sent to the "Old" register and a new word will be processed into the "New" register. If the transmission was without error, the receiving chip will signal for the new word. If errors were present, however, the receiving chip will signal for a retransmission of the previous word. This process will continue until the computer signals the end of the data string.

Specifications

Control for this system is determined by four basic inputs:




COUNTER: asserted by terminal before transmission

DATA_INCOMING: asserted by terminal when data is available to transmit

DATA_REQUESTED: asserted by receiving system when ready to receive data

NEW_DATA_DESIRED: asserted by receiving system when previous data is correct and it is ready for more data


Five basic outputs control the flow of data:




INPUT_LOAD: controls when the terminal begins transmitting data to the ACIA

NEW_REG_LOAD: controls the loading of data into an internal register and selects whether to transmit new or old data

OLD_REG_LOAD: controls the loading of old data into buffer register for possible retransmission

FLAG_ERROR: controls action when an incorrect signal is asserted

OUTPUT_DATA: controls the Counter PLA which controls of the flow of data from tranmitter to receiver


The block diagram and state diagram more clearly illustrates some of these functions.

Final Results

The final design of the ACIA consisted of one 7-bit register, two 8-bit registers, eight 2:1 multiplexors, one data compression and error coding module, one master PLA, one counter PLA and one parallel to serial shift register. This is the actual layout of the final design. Twenty two I/O pins were used in all for Vdd, ground, seven input bits, and control logic from the terminal and Chip 2. Clocking was done with a multiphase two clock system. The flow of data through the registers was controlled by a qualified Clock A signal, while the parallel to shift register was run by alternating Clock A and Clock B signals. Simulation was done on the IRSIM software package. Two seven bit inputs were made and the New_Data_Desired and Old_Data_Desired signals were then asserted to test the data flow through the system. The final outputs were correct.

Test Results

Simulation was done with the IRSIM software package. Two seven bit inputs were made and the New_Data_Desired and Old_Data_Desired signals were then asserted to test the data flow through the system. The final outputs were completely as expected for the two comprehensive test vectors which were used in simulation. These test vectors will be described more fully in the final results section. The IRSIM output is used for comparison.

The chip returned from fabrication had forty pins for use, although six are pre- allocated for power and ground interconnects. Our project used twenty of the pins, thirteen of which were input and seven output. Testing was performed using Omnilab.

We tested the chips using two test vectors which cover a large variety of state- to-state transitions.

Three of the four chips tested performed exactly as expected when tested. The fourth chip also performed with moderate success. When tested, the fourth chip transitioned between states as expected and generated correct outputs at six of the seven pins. Unfortunately, the pin which failed was the output_data pin, which sends out the encoded serial data stream. From a design stand- point, this pin is one of the most important. The output from this pin was a constant stuck at 0 in Omnilab. This would tend to imply that failure was due to either disconnection between the wafer to the output pin or some sort of internal flaw probably in the parallel-to-serial shift register. An error in the pad frame may have also caused the glitch.

The chip tests yielded results which are identical in nature to the results prev ously acquired using IRSIM.

Before chip testing, we expected a maximum chip speed of 23.45 MHz. Our belief after simulation was that the longest path through the chip was within the parallel-to-serial shift register. Upon testing, the chips responded correctly to input clock speeds of up to 17 MHz. When divided into two-phase non overlapping clock intervals, this indicated a maximum performance frequency of 4.25 MHz. When the clock speeds were increased to 34 MHz, the chips performed very nearly perfectly to the test vectors except at one point, one of the output_data bits was wrong.

The results lead to two conclusions. First, the chips probably perform at a moderately higher frequency than indicated here. This belief is because our testing was limited because of a maximum rating in the padframes to 15 MHz and inability to vary the Omnilab stimulus to frequencies between 17 MHz and 34 MHz. Second, the apparently vindicates our original belief that the slowest path is within the parallel to serial shifter. This is because the data bits are processed by the shift register just before being sent out for transmission. The shift register affects data bits only, and would not be expected to affect state transitions within chip which would lead to otherwise erratic behavior.

Conclusions

We met all of our original design goals, although the failure of the second chip was unexpected. Unfortunately, we overestimated the speed capabilities of our chip, although this didn't hinder the chip's performance.




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zaphod@rice.edu / jenief@rice.edu / blarney@rice.edu