ELEC 422 VLSI Design: Group E

Arpit Shah, James Carson, and Lars Petter Eliassen

Currently we are at Rice University. working on B.S.'s in Electrical Engineering(systems) scheduled to be completed in the Spring of 1996.

We are stage-2 of a two stage project which simulates segments of a modem to beeper message system.

To learn about stage-1 of our project please look at Group D.

INTRODUCTION AND SUMMARY

In today's rapidly evolving communication industry, the field of wireless communication is booming. Regular numeric pagers have been available for decades, but lately, alphanumeric pagers have been introduced. These pagers represent an important expansion of the market. In combination with our sister-group's chip, our design represents one approach to alphanumeric pagers that provides the basic functionality of an alphanumeric pager, with the exception of the receiver/transmitter link. The purpose of our project is to design a chip that simulates segments of a modem to beeper system. In particular, our chip acts as part of the second stage of a communications system, interfacing with our sister group's encryption chip. As seen on the block diagram below, external components such as a terminal/computer, Liquid Crystal Display (LCD), and some form of receiver/transmitter are necessary blocks in the communication system.

The inputs to our chip will be a bitstream of characters and handshaking signals sent to us either by the stage-1 chip or some other communication system. In order to communicate with the state-1 chip, we use so-called batch-handshaking, where the a retransmission request is issued only after an entire character has been transmitted. Also, the chip can use continuous handshaking, where retransmission requests are issued after each clock-cycle. The chip outputs a character to a Liquid Crystal Display. Currently, our chip can only display one character at a time. However, our design can easily be expanded to display many characters.

FUNCTIONAL DESCRIPTION:

During normal operation, the finite state machine (FSM) pla activates the load signals for the series-parallel register at the appropriate time to receive bitstream data. The parity of the error is checked. If there is no parity error, then the FSM activates the load signal for the 6-bit parallel register to protect the encoded ascii data from the next incoming signal. The outputs of the parallel register are connected to a 6-bit to 14-bit MPLA decoder. The output of the MPLA is connected to a 14-bit parallel register. There are actually two 14-bit parallel registers in series. When the FSM activated the load signal of the 6-bit parallel register, it also activated the Shift PLA. When activated, the Shift PLA sends signals to the 14-bit parallel registers. Essentially, data in the second 14-bit parallel register is replaced with the data in the first 14-bit parallel register. Then the data in the first 14-bit parallel register is replaced by the data coming out of the MPLA. In this way the current and previous signals are always stored. The MUX selects which of the the 14-bit parallel register outputs go to the pin outputs of the chip. This MUX selection is governed by a Toggle PLA, which in turn is controlled by a TOGGLE input. The user can switch between the current and previous character being displayed on the LCD with the press of a button. If the logistics of the pad frame allowed, it would be easy to add more 14-bit parallel registers and have each output to its own LCD. Thus multiple characters could be displayed at the same time. There are two types of handshaking with the first stage that this chip can handle. The type is selected by the value of the mode, MD. When mode is zero, batch handshaking is utilized. This means that stage-1 checks after the signal has been sent whether the same signal needs to be sent again. So during batch handshaking, this chip waits till stage-1 is ready before sending the request for the old signal. In continuous handshaking, mode one, the first stage is always ready to stop transmission and start over whenever this stage makes the request to do so. The FSM handles all of the handshaking.

PIN LAYOUT:

There are forty I/O pads around the perimeter of the padframe. We use all of them. Two are for inputs from stage-1, three are inputs from the user of stage-2. Fourteen are outputs to the LCD. Two outputs return to stage-1. Three pins are for ground, another three are for Vdd, and four are for CLKA and CLKB. The remaining pins are for diagnostics.

PLA DESCRIPTIONS Finite State Machine:

The finite state machine (FSM) governs the operation of the majority of the chip, as well as the interaction with the first stage. There are fourteen different states, and thirty-seven pathways between states. The RESTART input signal initializes the FSM to state0. To make sure that any data does not start being received in the middle of a transmission, the FSM waits for the CMD signal to drop low before proceeding to state1. At this point, when the CMD signal goes high, the FSM goes to state2 to begin reading in data from the bitstream. As long as the CMD signal stays high, bits will be read in and the FSM proceeds through the states sequentially up to state9. State10 is a dummy state, which exists only to make sure that the error checker has time to return its result. State11 checks ERR, and assuming no parity error, returns to state0 to begin the cycle again. This is unless the CMD signal has already dropped low, in which case there is no need to wait in state0 for the CMD signal to drop, so state11 goes directly to state1. If MD is low, and thus batch handshaking is selected, then at state9 the REPEAT bit is checked. REPEAT will be high if the CMD signal dropped low at any time during states2-8. If REPEAT is high, the FSM continues on to state12, which is similar to state0. During continuous handshaking, when MD is high, the FSM will immediately go to state13 whenever the CMD signal drops low while in states2-8. If a parity error is detected in state11, the FSM proceeds to either state12 or state13 depending on whether the CMD signal is high or low respectively. State specified outputs The FSM sets RDY and NEW high while in state1, since it is ready for a new bitstream to be sent. RDY is set high and NEW is set low in state13 as at that point the chip desires an old signal. At all other states, RDY is set low, and the state of NEW is irrelevant. States2-9 each specify a different load bit for the series-parallel registers for acquiring bits from the bitstream. If no parity error is detected in state11, then L2 is set high, which loads the parallel registers and activates the Shift PLA. All other times L2 is low. There are thirty-seven different pathways in the FSM. Six irsim simulations are used to demonstrate these. The description of these simulations follows.

Shift PLA: Description of Operation The purpose of the Shift PLA is to load the 14-bit parallel registers properly so that the current and previous characters are stored at all times. Whenever a new successful transmission arrives, Shift is triggered by the FSM. Shift then loads the second parallel register (SHIFT2) with the data in the first, and then proceeds to load the first register (SHIFT1) with the data from the MPLA.

Toggle PLA: Description of Operation The Toggle PLA simply sends the correct signals to the MUX to select which character, the previous or the the current, is sent to the output pins. It is controlled by the TOGGLE input. If the TOGGLE input were to be directly run into the mux, the user would have to hold down the TOGGLE button to see the previous character. The Toggle PLA allows the user to just press down the toggle button for an instant or more to switch which output is being displayed. Holding down the button will not rapidly switch between which character is being output, since the Toggle PLA has four states, allowing such undesireable behavior to be suppressed.

MPLA Description The MPLA decodes the incoming 6-bit character into a 14-bit representation that controls the LCD. Each of the 14 bits represents one segment of the display. Characters represented are A-Z, 0-9, and the special characters ? / + - ' . Any encoded ascii input that does not map to one of the aformentioned characters is mapped to * . To check that our 14-bit representations were correct, we used Matlab to visually display the characters. We also wrote a program to check if any of the 6 input bits would be a sufficient specification for any of the 14 output bits. No such simple input-output mappings were discovered.

Performance Analysis The main concern with performance timing was whether the latches in the series register could store the incoming series bitstream. With each bit being output from stage-1 as VbSa we were required to latch each bit with minimum delay. The loads from the stage-2 FSM were also VbSa and being ANDed with CLKA to produce a Qa store. Critical path for the circuit in IRSIM was 2.5 nsec for the store of latch7 on a fall. CRYSTAL gives a critical path of 6.55 nsec, which is still within the 12 nsec clocking protocol. Another concern was whether the error signal from the parity check would be valid in time for the FSM to evaluate a REPEAT or ALL-CLEAR state. CRYSTAL runs produced 19.3 nsec maximum delays. Because at CLKA9 the signal would not be valid since we were still latching bit7 (reference 4.1 System Timing Diagram) we decided to add a dummy cycle and assume the signal would be valid on CLKA10. CRYSTAL and IRSIM give no problems since critical path is under the clocking protocol and we are given an entire clockcycle to evaluate the error combinational logic which is independent of clocking. The timing is airtight if CLKA has a minimum bandwidth of 10 nsec which is smaller than the minimum clockwidth required by STAGE-1. Since both stages are synchronous we adopt the largest timing protocol. Summary This chip contains 3723 transistors; 2377 n-channel and 1346 p-channel.