MASK Processor

Designed By

  • Das, Suman
  • Kallahalla, Mahesh
  • Rix, Mark
    x3629
We will like to design a simple 4-bit RISC processor. The RISC properties to be used are:
  • Hard-wired control unit
  • Single cycle execution (except load/store),
  • Reg-reg load/store architecture,
  • Fixed instruction size (except load/store).
  • The design will use 8 general purpose registers and 1 special purpose register. The word size will be 12-bits with a 12-bit extension for load/store operations. Instruction set architecture will be limited to 16 instruction including simple arithmetic, logic and branch instructions. Our architecture will assume separate data and code memories each addressable up to 256Bytes.
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