Elec 422, VLSI Design I: Fall 1995, Course Information

Rice University
Elec 422, VLSI Design I
Course Information, Fall 1995

Organization

Day & Time: TTh 2:30-3:50pm
Location: Abercrombie Lab A126
Instructor: Joe Cavallaro, AL A224, x4719, cavallar@rice.edu
VLSI Lab: Abercrombie A121, 8 color Xterminals (Owlnet)
Lab Assistant: Chaitali Sengupta, AL A211, x3222, chaitali@rice.edu

Topics

Logic Design and Simulation.
CMOS Processing.
``Stick'' Diagrams.
Hierarchical Layout Methodology.
State Machine Design and Programmable Logic Arrays.
Design for Testability; Fault Tolerance.
Computer-Aided Design Tools: irsim, magic, spice...
MOSIS Scalable CMOS Design; nwell process.

Required Textbooks

1. Weste & Eshraghian ``Principles of CMOS VLSI Design'' Second Edition, Addison-Wesley, 1993.
2. VLSI Design I Packet (Available at Rice Campus Store Textbook Service Counter)

Course Requirements

• Students are required to enroll in Elec 423 VLSI Design II during Spring 1996. This is due to contractual obligations with the MOSIS Fabrication Service to provide a report on the success of the fabricated chip.
• Group Project (Groups of three) to be fabricated by MOSIS.
• Five Homeworks during first half of semester. (Independent work under the Honor System is expected).
• Midterm Exam (In-class, Honor System, closed book, late-October).
• Project Presentation & Design Review (Last week of class).
• Final Group Project Report (Due Friday Dec. 8).

About this document ...

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