Welcome to the VLSI Design II class at Rice University
Elec 423 at Rice is a continuation of
Elec 422 (VLSI Design I).
The focus of Elec 423 is VLSI testing centered around testing
of the first semester original design projects which have been fabricated
by the MOSIS Service.
Students will perform functional and high-speed testing of the chips.
The chips are expected to arrive in mid-March.
MOSIS Run Status
The fall 2000 projects are being fabricated using the
AMI 1.5 micron and AMI 0.5 micron CMOS processes through MOSIS.
Class AMI 1.5 micron projects are included in the T11X MOSIS run.
Current run status info is
here.
Class AMI 0.5 micron projects are included in the T11Z MOSIS run.
Current run status info is
here.
Course Contents
The topics covered in this course include:
- VLSI testing and test generation, including Test Access Port (TAP).
- Creation of a basic standard cell library from layout leafcells.
- Software for automatic test generation.
- Use of FPGAs for design verification.
- Manufacturability and manufacturing yield analysis.
- Economics and cost factors in VLSI ASIC design and manufacturing.
- Chip inspection using optical microscopy.
Test Equipment
The functional testing will be performed using
specially equipped computers.
Orion Omnilab test stations are attached to three PC's
in the VLSI Design Center, Abercrombie Labs AL A117.
These PC's are networked and the test vector files prepared
for Irsim can be converted to Omnilab format.
A breadboard and connectors will be issued to the students.
High speed testing can also be done with Omnilab up to about 17 MHz.
About the Elec 422, VLSI Design I, class in
Fall 2000 (last term).
Joe Cavallaro
Last modified: 21 January 2001