Next: Introduction
Automated Evaluation of Critical Features in VLSI Layouts Based on
Photolithographic Simulations
Joseph R. Cavallaro, Chaitali Sengupta,
Frank K. Tittel, and William L. Wilson, Jr.
Rice University
Department of Electrical and Computer Engineering
P.O. Box 1892, Houston, TX 77251
Abstract:
This paper describes a CAD tool (An Integrated CAD Framework)
which links VLSI layout editors to
lithographic simulators and provides information on the simulated
resolution of a feature to the circuit designer.
The designer can modify the original layout based upon this analysis
to create compact circuits with better yield capabilities.
The objective of this project is to improve the manufacturability
of high density VLSI intergrated circuits.
Joe Cavallaro
Fri Nov 24 16:58:55 CST 1995