Status Report

Status of Project

Rowboat Encryption Chip
http://www.owlnet.rice.edu:80/~pickettc/elec422/status.html Frank Alejano
John Cusey
Chris Pickett

I. What We Have Done

At this point, we have defined the functionality of the chip (we want it to do encryption), we have defined the algorithm that we will be using to do the encryption, we have defined (in general terms) what the finite state machine that will be doing the control will be doing -- what control signals are necessary and when they will be asserted and deasserted, etc. In addition, we have drawn a preliminary layout for the chip, meaning that we have figured out what each of the major subblocks will be, how large they will be, and where they will be located in teh final layout. All of this is stuff that we have reported on in other places.

Since our last report, we hve begun to do two things. 1) We have begun to do higher-level layout. Previously, we had a number of standard cells, such as the 2-input NAND and NOR, the XOR, the latch, the inverter, the transmission gate, and so on. We are are using these standard cells to build up higher-level blocks. Specifically, our project requires several 8- and 12-bit latches (to latch the input, the output, and the intermediate stages, among other things), and 12-bit XORs. We have built these standard cells. 2) We have begun to do the meg coding for the control PLA. Due to the large number of states that our control FSM has, this is a somewhat long process, but at least we have begun.

II. What We Have Yet To Do

We have not finished the control PLA, obviously, and that is high on our list of priorities. In addition, we need to write a C program that will perform the encryption algorithm on data we enter and spit out the encrypted form. This is necessary since it is not intuitively obvious from looking at the output of an encryption chip whether the encryption has been performed correctly. Due to the relative simplicity of the DES-like algorithm that we are using, this should not be hard to do. In any case, we do not need it yet since we are not ready to test our design.

The plan for the next couple of weeks is as follows: 1) Continue higher-level block development (specifically, we will need to construct a barrel shifter, an 8-bit multiplexer, and an 8-bit demultiplexer, in addition to the 8- and 12-bit registers and 12-bit XORS that we have already constructed; 2) Complete the meg coding of the control PLA and test it for basic functionality; 3) Write the C test program; 4) Synthesize even higher-level blocks, like the block that will take the input serially by bytes and put it into the input registers.

October 26, 1995