The project involves the VLSI implementation for, 8-bit, radix-2 division of two unsigned integers using a non-restoring division algorithm.

The system involves an adder, shift register and other registers. The functional blocks are shown in figure 1.

The nonrestoring algorithm for computing a/b , where "a" is stored in A(dividend) register, "b" is stored in B(divisior) register and 0 is stored in P(quotient) register is:

If P is negative,

1a. Shift the register pair (P, A) one bit left. 2a. Add the contents of register B to P.

Else,

1b. Shift the register pair (P,A) one bit left. 2b. Subtract the contents of register B from P.

3. If P is negative, set the low-order bit of A to 0, otherwise set it to 1.

After 8 repetitions, the quotient is in A. If P is non-negative, it is the remainder. otherwise add "b" for the remainder. The result will be available in the form of an integer and a rounded off fraction.

A shift register is used for left shift. Subtraction is carried out using two's complement.

The system has a two phase clock, for a synchronous design. The inputs of the system are 8-bit data in, carry in and outputs are 8-bit data out and carry out.

Our goal was to implement an 8-bit ALU, supporting division, and including addition and subtraction. Logic is provided to choose the required operation. The outputs at the end of every state are available on the output pads for testability. A completion report sent to MOSIS is available for review.